A Low-Pin Count (LPC) bus is an internal-communication bus for computer systems and has been implemented in recent years to gradually replace the Industry Standard Architecture (ISA) bus. For example, the LPC Interface Specification 1.0 available from Intel Corporation of Santa Clara, Calif. calls for an LPC interface between a computer system's core logic chipset and motherboard I/O functions.
The LPC bus architecture is a serial, 7-pin simple bus with a 33 MHz clock. There are no defined slots, unlike the ISA and PCI buses, thus only on-board solutions are used in the LPC architecture. Since its speed is limited to 33 MHz, it is not designed for heavy-duty data transfer. Devices that are likely to be found on the LPC bus are legacy devices, such as Super I/Os, and flash boot devices. The LPC bus architecture is software transparent to higher level I/O functions and is compatible with existing peripheral devices and applications. The LPC bus, however, is not readily compatible with other bus architectures, such as register-based memory buses, because of the discrepancy in the bus speeds.
A system bus is a bus architecture designed to facilitate communication between a computer's central processing system and its register based memory system. The bus speed of a system bus is typically not quite as fast as the CPU speed, but is significantly faster than the speed of the LPC bus. As a result, communication between a system bus and an LPC bus cannot be achieved by a simple interface.
In the past, communication between devices that use the system bus and devices that use the LPC bus was indirect and required a significant firmware/software undertaking. This undertaking proved to require a substantially lengthy processing time. Therefore, a need has arisen to eliminate the substantial length of this undertaking by providing a direct path between the system and the LPC busses.